1 march 5, 2012 product brief ? 2012 integrated device technology, inc. dsc-7238/- synchronous ethernet wan pll and clock generation for ieee-1588 idt and the idt logo are trademarks of integrated device technology, inc. 82v3391 features highlights ? single chip pll: ? features 0.5 mhz to 560 hz bandwidth ? provides node clock for itu- t g.8261/g.8262 synchronous ethernet (synce) ? exceeds gr-253-core (oc-192) and itu-t g.813 (stm-64) jitter generation requirements ? provides node clocks for cellular and wll base-station (gsm and 3g networks) ? provides clocks for dsl access concentrators (dslam), espe- cially for japan tcm-isdn network timing based adsl equip- ments ? provides clocks for 1 gigabit and 10 gigabit ethernet application ? supports clock generation for ieee-1588 applications main features ? provides an integrated single-ch ip solution for synchronous equip- ment timing source, including stratum 3, stratum 4e, stratum 4, smc, eec-option 1 and eec-option 2 clocks ? supports 1pps input and output ? employs pll architecture to fe ature excellent jitter performance and minimize the number of external components ? integrates t4 dpll and t0 dpll; t4 dpll locks independently or locks to t0 dpll ? supports programmable dpll bandwidth (0.5 mhz to 560 hz in 19 steps) and damping factor (1.2 to 20 in 5 steps) ? supports 1.1x10 -5 ppm absolute holdover accuracy and 4.4x10 -8 ppm instantaneous holdover accuracy ? supports hitless reference switch ing to minimize phase transients on t0 dpll output to be no more than 0.61 ns ? supports programmable input-to- output phase offset adjustment ? limits the phase and frequency offset of the outputs ? provides out1~out7 output clocks whose frequency cover from 1pps to 644.53125 mhz ? includes 25 mhz, 125 mhz and 156.25 mhz for cmos outputs ? includes 25.78125 mhz, 128.90625 mhz and 161.1328125 mhz for cmos outputs ? includes 25 mhz, 125 mhz, 156.25 mhz, 312.5 mhz and 625 mhz for differential outputs ? includes 25.78125 mhz, 128.90625 mhz, 161.1328125 mhz, 322.265625 mhz and 644.53125 mhz for differential outputs ? provides out8 for composite cl ocks and out9 for 1.544 mhz/ 2.048 mhz (bits/ssu) ? provides in1 and in2 for composite clocks ? provides in3~in14 input clocks whose frequencies cover from 2 khz to 625 mhz ? includes 25mhz, 125 mhz and 156.25 mhz for cmos inputs ? includes 25mhz, 156.25 mhz, 312.5 mhz and 625 mhz for dif- ferential inputs ? internal dco can be controlled by an external processor to be used for ieee-1588 clock generation ? supports forced or automatic operating mode switch controlled by an internal state machine. automatic mode switch supports free- run, locked and holdover modes ? supports manual and automatic selected input clock switch ? supports automatic hitless selected input clock switch on clock fail- ure ? supports three types of input clock sources: recovered clock from stm-n or oc-n, pdh network sync hronization timing and external synchronization reference timing ? provides a 2 khz, 4 khz, or 8 khz frame sync input signal, and a 2 khz or 8 khz frame sync output signal ? provides a 1pps sync input signal, and a 1pps sync output signal ? provides output clocks for bits, gps, 3g, gsm, etc. ? supports ami, pecl/lvds and cmos input/output technologies ? supports master clock calibration ? supports master/slave applicati on (two chips used together) to enable system protection against single chip failure ? supports telcordia gr-1244- core, telcordia gr-253-core, itu-t g.812, itu-t g.8262. itu- t g.813 and itu-t g.783 recom- mendations other features ? multiple microprocessor interf ace modes: eprom, multiplexed, intel, motorola, i2c and serial ? ieee 1149.1 jtag boundary scan ? single 3.3 v operation with 5 v tolerant cmos i/os ? 100-pin tqfp package, green package options available applications ? 1 gigabit ethernet and 10 gigabit ethernet ? bits / ssu ? smc / sec (sonet / sdh) ? dwdm cross-connect and transmission equipment ? synchronous ethernet equipment ? central office timing source and distribution ? core and access ip switches / routers ? gigabit and terabit ip switches / routers ? ip and atm core switches and access equipment ? cellular and wll base-station node clocks ? broadband and multi-service access equipment
idt82v3391 product brief synchronous ethe rnet wan pll and clock generation for ieee-1588 description 2 march 5, 2012 description the idt82v3391 is an integrated, single-chip solution for the syn- chronous equipment timing source for stratum 3, stratum 4e, stratum 4, smc, eec-option1, eec-option2 clocks in sonet / sdh / synchro- nous ethernet equipment, dwdm and wireless base station. the device supports several types of input clock sources: recovered clock from synchronous ethernet, stm-n or oc-n, pdh network syn- chronization timing and external synchronization reference timing. the device consists of t0 and t4 pat hs. the t0 path is a high quality and highly configurable path to prov ide system clock for node timing synchronization within a sonet / sdh / synchronous ethernet network. the t4 path is simpler and less configurable for equipment synchroniza- tion. the t4 path locks independently from the t0 path or locks to the t0 path. an input clock is automatically or manually selected for t0 and t4 path. both the t0 and t4 paths support three primary operating modes: free-run, locked and holdover. in free-run mode, the dpll refers to the master clock. in locked mode, the dpll locks to the selected input clock. in holdover mode, the dpll resorts to the frequency data acquired in locked mode. whatever the operating mode is, the dpll gives a stable performance without being affected by operating condi- tions or silicon process variations. there are 2 high performance aplls that can be used for low jitter sonet and ethernet clocks the device provides programmable dpll bandwidths: 0.5 mhz to 560 hz in 19 steps and damping factors: 1.2 to 20 in 5 steps. different settings cover all sonet / sdh cl ock synchronization requirements. a highly stable input is required for the master clock in different appli- cations. the master clock is used as a reference clock for all the internal circuits in the device. it can be calibrated within 741 ppm. all the read/write registers are accessed through a microprocessor interface. the device supports si x microprocessor interface modes: eprom, multiplexed, intel, motorola, i2c and serial. in general, the device can be used in master/slave application. in this application, two devices should be used together to enable system protection against single chip failure.
idt82v3391 product brief synchronous ethe rnet wan pll and clock generation for ieee-1588 functional block diagram 3 march 5, 2012 functional block diagram ex_sync1 monitors t0 pfd & lpf divider t4 pfd & lpf divider apll microprocessor interface jtag phase offset 77.76 mhz auto divider divider out3 out3 mux divider out4 out4 mux out5 out6 out6 mux out7 out7 mux divider out2 out2 mux divider out1 out1 mux out5 mux out8 out9 mux t4 apll mux t0 apll mux t4 input selector t0 input selector osci 77.76 mhz 16e1/16t1 12e1/gps/e3/t3 16e1/16t1 12e1/24t1/e3/t3 out8 mux auto divider out9 mux auto divider auto divider 12 12 12 12 12 12 12 t0 dpll t4 dpll selection input in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 in11 in12 in13 in14 frsync_8k_1pps mfrsync_2k_1pps output gsm/gps/16e1/16t1 from t0 77.76 mhz from t4 77.76 mhz from t0 16e1/16t1 from t4 16e1/16t1 t0 77.76 mhz t0 8 khz gsm/obsai/16e1/16t1 8 k divider input pre-divider priority input pre-divider priority input pre-divider priority input pre-divider priority input pre-divider priority input pre-divider priority input pre-divider priority input pre-divider priority input pre-divider priority input pre-divider priority input pre-divider priority input pre-divider priority input pre-divider priority input pre-divider priority divider divider divider eth eth t0 apll t4 apll
idt82v3391 datasheet synchronous etherne t wan pll and clock ge neration for ieee-1588 4 march 5, 2012 ordering information xxxxxxx xx x device type blank process / temperature range 82v3391b industrial (- 40 c to + 85 c) wan pll eqg green thin quad flatpack ( tqfp, eqg100)
idt82v3391 product brief synchronous etherne t wan pll and clock ge neration for ieee-1588 5 march 5, 2012 disclaimer integrated device technology, inc. (idt) and its subs idiaries reserve the right to modify the products and/or specif ications described herein at any time and at id t?s sole discretion. all information in this doc- ument, including descriptions of product feat ures and performance, is subject to cha nge without notice. performance specificati ons and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provide d without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s produc ts for any particular purpose, an implie d warranty of merchantability, or non-infrin gement of the intellectual property rights of others . this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly af fect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2012. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution
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